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Languguage OS II Version 10-94 (Knowledge Media)(1994).ISO
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c32src.arc
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RESETV.SA
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1991-03-01
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** Set checksum at "CHECKVAL" below! **
TTL Reset Vector and Code Size
OPT P=68332
******************************************************************************
** Exported portion ***
*V****************************************************************************
*** ***
*** MODULE: ***
*** RESETV - This module contains the reset vector for the system. ***
*** It also includes a longword that contains the size of ***
*** the code segment in bytes and all of the user custom- ***
*** ization parameters. ***
*** ***
*** ENVIRONMENT: ***
*** M68300 BCC EVM system ***
*** ***
*** LANGUAGE: ***
*** M68MASM for MS-DOS MC68332 assembly language relocatable module ***
*** ***
*** SUMMARY OF CONTENTS: ***
*** <will be linked to start at $E0000 for BCC> ***
*** System reset vector. ***
*** Code segment size. ***
*** User customization parameters. ***
*** ***
*** NOTES: ***
*** 1. Source equivalent copy of CPU32Bug parameter area for Motorola ***
*** FREEWARE Bulletin Board System (BBS) to produce object ***
*** equivalent code. See REVISION HISTORY below for version nbr. ***
*** 2. This source code can be freely used at no cost/obligation, ***
*** i.e. it is PUBLIC DOMAIN software. Please report any errors/ ***
*** additions to the SYSOP of the Motorola FREEWARE BBS. ***
*** 3. Parameters which reference linker symbols (XREF/XDEF) will ***
*** not be defined until link time, so the obj. code listed here ***
*** will not match the actual EPROM code. ***
*** ***
*^****************************************************************************
*** INTERNAL PORTION OF THE MODULE HEADER ***
******************************************************************************
*** ***
*** REVISION HISTORY (add changes to the top): ***
*** ***
*** DATE AUTHOR CHANGES ***
*** ---------- --------------- ------------------------------------- ***
*** 03/01/91 Peter S. Gilmour Compatible with CPU32Bug version 1.00. ***
*** 05/02/90 Peter S. Gilmour Compatible with 332Bug version 1.02. ***
*** 01/16/90 Peter S. Gilmour Initial version port to MS_DOS based ***
*** M68MASM from original source code. ***
*** Compatible with 332Bug version 1.01. ***
*** ***
******************************************************************************
*** ***
*** XDEFS: ***
*** ***
XDEF ORIGIN Start of program space
XDEF CODESIZE Size of program space in bytes
XDEF CHECKSUM Permit access by confidence test
* Old CSn base addr reg. values
XDEF .CSBAR0,.CSBAR1,.CSBAR2,.CSBAR3,.CSBAR4,.CSBAR5
XDEF .CSBAR6,.CSBAR7,.CSBAR8,.CSBAR9,.CSBAR10
* Old CSn base addr reg. values
XDEF .CSOR0,.CSOR1,.CSOR2,.CSOR3,.CSOR4,.CSOR5
XDEF .CSOR6,.CSOR7,.CSOR8,.CSOR9,.CSOR10
* Common CSBOOT values
XDEF .CSBARBT Old/new CSBOOT base addr reg. value
XDEF .CSORBT Old/new CSBOOT option reg. value
* New CSn base addr reg. values
XDEF CSBAR0$,CSBAR1$,CSBAR2$,CSBAR3$,CSBAR4$,CSBAR5$
XDEF CSBAR6$,CSBAR7$,CSBAR8$,CSBAR9$,CSBAR10$
* New CSn base addr reg. values
XDEF CSOR0$,CSOR1$,CSOR2$,CSOR3$,CSOR4$,CSOR5$
XDEF CSOR6$,CSOR7$,CSOR8$,CSOR9$,CSOR10$
XDEF MCR_OR MCR bits to add at power-on
XDEF MCR_AND MCR bits to delete at power-on
XDEF .PICR Periodic interrupt control reg. value
XDEF .PITR Periodic interrupt timer reg. value
XDEF RB_SP Rom Auto Boot SP location in ROM
XDEF RB_PC Rom Auto Boot PC location in ROM
XDEF CONSCI Console default SCI parameter table
XDEF .PARMS SCI parameter definition
XDEF .BAUD SCI baud rate value
XDEF .PARITY SCI parity value
XDEF .DATA SCI nbr. data bits value
XDEF .STOP SCI nbr. stop bits value
XDEF .XON_ENB SCI XON/XOFF enable value
XDEF .XON SCI XON value
XDEF .XOFF SCI XOFF value
XDEF SYPCR_OR SYPCR bits to add at power-on
XDEF SYPCR_AND SYPCR bits to delete at power-on
XDEF FEXTAL External clock frequency (in Hz)
XDEF FCRYSTAL Crystal frequency (in Hz)
XDEF PWR_ON Start of Power on branch vectors
XDEF PWR_TBL1 Init. Table #1 Power on branch vector
XDEF PWR_INI MCU init. Power on branch vector
XDEF PWR_TBL2 Init. Table #2 Power on branch vector
XDEF PWR_TTL Sign on title Power on branch vector
XDEF PWR_TST Self-test Power on branch vector
XDEF PWR_GO System Go Power on branch vector
XDEF INITTBL Initialization Table
XDEF INITTBLE Initialization Table end
XDEF SIGNON Offset to system sign on message text
*** ***
*** XREFS: ***
*** ***
XREF CONFTST Confidence test entry point
XREF SYSINIT Start of program (system init.)
XREF INIT_CS MCU initialization (chip selects, etc.
XREF INIT_T1 Table #1 Initialization
XREF INIT_T2 Table #2 Initialization
XREF MEMPAGE 16 Megabyte page
*** ***
*** Local macros: ***
*** ***
VECTOR MACRO ! SETUP VECTOR SPACE
SECTD SET 0 ! DEFINE DATA SECTION
SECTP SET 8 ! DEFINE PROGRAM SECTION
SECTION SECTP ! PUT USER INTO PROG. SECTION
ENDM !
***
*** Local equates:
***
CR EQU $0D ASCII carriage return
LF EQU $0A ASCII line feed
SPACE EQU $20 ASCII space
*
* For M68300 BCC and PFB.
*
* NOTE: Unused upper address lines are specified as 1's so ABSOLUTE SHORT
* addressing (sign extension) can be used.
*
SR_VAL EQU $2700 status register initial value.
RAM_BASE EQU $0 BCC RAM base address
RAM_SIZE EQU $10000 BCC RAM size (bytes)
ROM1_BASE EQU $E0000 BCC EPROM base address
ROM1_SIZE EQU $20000 BCC EPROM size (bytes)
IRAM_BASE EQU $40000
FPCP_BASE EQU $FFFFE800 PFB MC68881/MC6882 base address
* . (Floating Point Co-Processor)
FCRYSTVAL EQU 32768 Crystal frequency (in Hz)
HI_BASE EQU $FFFFF000 CPU32 module (registers) base high addr
* . This is the default used at power-up!
LO_BASE EQU $007FF000 CPU32 module (registers) base low addr
SIM EQU $A00 CPU32 System Integration Module base addr
RAMCR EQU $B00 CPU32 RAM Control Module base offset
QSM EQU $C00 CPU32 Queued Serial Module base offset
AUTO_BASE EQU $FFFFF800 Autovector base address
* Define bits for Power Up Status (PWRSTATUS) flag:
EXTAL_BIT EQU 31 External Clock flag bit: 0= off (VCO)
CHKSUM_BIT EQU 30 Checksum not pgm'd yet bit: 0= pgm'd
LOCALRAM EQU RAM_BASE base of local RAM
SYSRAMSZ EQU $00004000 size of local RAM (for system use)
LCLRAMMX EQU RAM_SIZE max size of local RAM (for M68332 BCC)
USRRAM EQU LOCALRAM+SYSRAMSZ base of user RAM
USRRAMSZ EQU LCLRAMMX-SYSRAMSZ size of user RAM
RAMSTART EQU LOCALRAM alias for base of local RAM
LOCALROM EQU ROM1_BASE base of local ROM (use PC rel refs!)
LCLROMSZ EQU $00010000 size of local ROM used by 332Bug
ROMUNPGM EQU $FF unprogrammed state of a byte of EPROM
FILL.1 EQU ROMUNPGM fill value for 1 byte = BYTE
FILL.2 EQU FILL.1<<8+FILL.1 fill value for 2 bytes= WORD
FILL.4 EQU FILL.2<<16+FILL.2 fill value for 4 bytes= LONG WORD
RAM2_BASE EQU LOCALRAM+LCLRAMMX Next RAM base address
ROM2_BASE EQU ROM1_BASE+ROM1_SIZE Next ROM base address
VECTSIZ EQU $400 Vector table size
USERLEN EQU $1000 user space reserved
MEMINC EQU $4000 memory increment for 130's or EVM's
STKLEN EQU MEMINC-USERLEN-VECTSIZ-4 size of bug/diag stack + static vars
*
* Interrupt levels & vectors
*
ABORTLVL EQU 7 abort level
ABORTVEC EQU 31 abort vector
ACFAILVL EQU 7 AC-Fail level
ACFAILVC EQU 65 AC-Fail vector
TIMERLVL EQU 6 timer level: M68332 periodic int. timer
TIMERVEC EQU 66 timer vector
*
* Setup Base Addresses:
* 1. A31-A24 must= 0 (MC68332 only uses A0-A23; rest are unused!)
* 2. A10-A0 must= 0 (for Base Address Register usage).
*
ADDRMASK EQU $00FFF800 Address mask (24-bits, A10-A0= 0)
RAM EQU RAM_BASE&ADDRMASK Setup Base Addresses
ROM EQU ROM1_BASE&ADDRMASK Setup Base Addresses
RAM2 EQU RAM2_BASE&ADDRMASK Setup Base Addresses
ROM2 EQU ROM2_BASE&ADDRMASK Setup Base Addresses
FPCP EQU FPCP_BASE&ADDRMASK Setup Base Addresses
IRAM EQU IRAM_BASE&ADDRMASK Setup Base Addresses
AVEC_7 EQU AUTO_BASE&ADDRMASK Setup Base Addresses
CSBAR_XX EQU $0000 Reset (unused) value for CSBARn
CSOR_XX EQU $0000 Reset (unused) value for CSORn
*
* Option Register Equates (CSORBT, CSORn):
*
B2K EQU 0 2K block size
B8K EQU 1 8K block size
B16K EQU 2 16K block size
B64K EQU 3 64K block size
B128K EQU 4 128K block size
B256K EQU 5 256K block size
B512K EQU 6 512K block size
B1M EQU 7 1MB block size
ASYNC EQU $0000 Asynchronous mode
SYNC EQU $8000 Synchronous mode
CS_UPPB EQU 2*$2000 Upper byte
CS_LOWB EQU 1*$2000 Lower byte
CS_BOTHB EQU 3*$2000 Both bytes (upper or lower)
CS_R EQU 1*$800 Read
CS_W EQU 2*$800 Write
CS_RW EQU 3*$800 Read or write
CS_AS EQU 0*$400 Address Strobe (AS*)
CS_DS EQU 1*$400 Data Strobe (DS*)
CS_FAST EQU 14 Fast termination DSACK*
CS_EXT EQU 15 External termination DSACK*
CS_WAIT EQU 1*$40 Wait cycles for DSACK*
CS_CSP EQU 0*$10 CPU space
CS_USP EQU 1*$10 User space
CS_SSP EQU 2*$10 Supervisor space
CS_SUSP EQU 3*$10 Supervisor/User space
CS_LVL EQU 1*$2 Interrupt priority level
CS_AVEC EQU 1 Autovector enable
* Select value for checksum below:
* - place "*" in front of the one you DON'T want assembled
*
*CHECKVAL EQU FILL.2 Checksum value for debugging
CHECKVAL EQU $3033 Checksum value for finished product
* . - must not be same as FILL.2!
* The actual value of the checksum word is not known at the time
* that this file is assembled or linked. However, an "intelligent"
* checksum method is used whereby the program tells the user what
* the checksum should be if the checksum hasn't been programmed yet!
* Make the change, re-make the program, and blow new EPROM.
*
* The checksum word consists of two bytes that are placed at offset
* locations $0E-0F in the Bug EPROM and is used during execution of
* the confidence check to validate the EPROM contents.
*
********************************
** Configuration Parameters **
********************************
* DO NOT ALTER! Must match with user documentation!
*
VECTOR
*
ORIGIN EQU *
PWR_SSP DC.L LOCALRAM+VECTSIZ+STKLEN Init. SSP = below user ram
PWR_PC DC.L PWR_ON Init. PC = power on branch vector
**
CODESIZE DC.L ROM1_SIZE Set Code Size (in bytes)
SRECMAX DC.B 32 Maximum # data bytes to put in S-records
* . Valid range= 1..250 (includes S3,S7)
* . (used by DU command)
CHECKALT DC.B FILL.1 -- reserved -- (alternate checksum)
CHECKSUM DC.W CHECKVAL Allocate space for checksum word
* . If CHECKVAL = FILL.2, then change
* . value of CHECKALT location!
* NOTE: "/256" is used in the Chip Select Tables below to shift address bits
* A23-A11 to bit positions B15-B3 (23-15= 8 bits = 256) for use in the
* SIM Base Address Registers.
*----------------------------------------------------------------------------
* Old Chip Select Table: (Rev. A BCC + Rev. A PFB)
*
.CSBAR0 DC.W RAM/256+B64K CS0 base & option register values
.CSOR0 DC.W 0*CS_WAIT+CS_UPPB+CS_RW+CS_AS+CS_SUSP
.CSBAR1 DC.W RAM/256+B64K CS1 base & option register values
.CSOR1 DC.W 0*CS_WAIT+CS_LOWB+CS_RW+CS_AS+CS_SUSP
.CSBAR2 DC.W RAM2/256+B64K CS2 base & option register values
.CSOR2 DC.W 1*CS_WAIT+CS_BOTHB+CS_R+CS_AS+CS_SUSP
.CSBAR3 DC.W RAM2/256+B64K CS3 base & option register values
.CSOR3 DC.W 0*CS_WAIT+CS_LOWB+CS_W+CS_AS+CS_SUSP
.CSBAR4 DC.W ROM2/256+B128K CS4 base & option register values
.CSOR4 DC.W 1*CS_WAIT+CS_UPPB+CS_RW+CS_AS+CS_SUSP
.CSBAR5 DC.W ROM2/256+B128K CS5 base & option register values
.CSOR5 DC.W 1*CS_WAIT+CS_LOWB+CS_RW+CS_AS+CS_SUSP
.CSBAR6 DC.W FPCP/256+B2K CS6 base & option register values
.CSOR6 DC.W CS_EXT+CS_BOTHB+CS_RW+CS_AS+CS_SUSP
.CSBAR7 DC.W CSBAR_XX CS7 base & option register values
.CSOR7 DC.W CSOR_XX . -- unused --
.CSBAR8 DC.W AVEC_7/256 CS8 base & option register values
.CSOR8 DC.W 0*CS_WAIT+CS_BOTHB+CS_R+CS_AS+CS_CSP+7*CS_LVL+CS_AVEC
.CSBAR9 DC.W CSBAR_XX CS9 base & option register values
.CSOR9 DC.W CSOR_XX . -- unused --
.CSBAR10 DC.W RAM2/256+B64K CS10 base & option register values
.CSOR10 DC.W 0*CS_WAIT+CS_UPPB+CS_W+CS_AS+CS_SUSP
*----------------------------------------------------------------------------
* Common Chip Select Table: (Rev. A BCC + Rev. A PFB) & (Rev. B BCC + Rev. B PFB)
*
.CSBARBT DC.W ROM/256+B128K CSBOOT base & option register values
.CSORBT DC.W 2*CS_WAIT+CS_BOTHB+CS_R+CS_AS+CS_SUSP
* - "2*CS_WAIT" = 2 wait cycles = AMD 27C1024-205LC 200 ns EPROM
* This EPROM is 2 wait cycles because it is always enabled, whereas the
* EPROM on the platform board (PFB) must first be enabled so it requires
* 3 wait cycles!
*----------------------------------------------------------------------------
* New Chip Select Table: (Rev. B BCC + Rev. B PFB, or later!)
*
CSBAR0$ DC.W RAM/256+B64K CS0 base & option register values
CSOR0$ DC.W CS_FAST+CS_UPPB+CS_W+CS_AS+CS_SUSP
CSBAR1$ DC.W RAM/256+B64K CS1 base & option register values
CSOR1$ DC.W CS_FAST+CS_LOWB+CS_W+CS_AS+CS_SUSP
CSBAR2$ DC.W RAM/256+B64K CS2 base & option register values
CSOR2$ DC.W CS_FAST+CS_BOTHB+CS_R+CS_AS+CS_SUSP
CSBAR3$ DC.W CSBAR_XX CS3 base & option register values
CSOR3$ DC.W CSOR_XX . -- unused --
CSBAR4$ DC.W AVEC_7/256 CS4 base & option register values
CSOR4$ DC.W 0*CS_WAIT+CS_BOTHB+CS_R+CS_AS+CS_CSP+7*CS_LVL+CS_AVEC
CSBAR5$ DC.W FPCP/256+B2K CS5 base & option register values
CSOR5$ DC.W CS_EXT+CS_BOTHB+CS_RW+CS_AS+CS_SUSP
CSBAR6$ DC.W ROM2/256+B128K CS6 base & option register values
CSOR6$ DC.W 3*CS_WAIT+CS_LOWB+CS_RW+CS_AS+CS_SUSP
CSBAR7$ DC.W ROM2/256+B128K CS7 base & option register values
CSOR7$ DC.W 3*CS_WAIT+CS_UPPB+CS_RW+CS_AS+CS_SUSP
CSBAR8$ DC.W RAM2/256+B64K CS8 base & option register values
CSOR8$ DC.W 1*CS_WAIT+CS_BOTHB+CS_R+CS_AS+CS_SUSP
CSBAR9$ DC.W RAM2/256+B64K CS9 base & option register values
CSOR9$ DC.W 0*CS_WAIT+CS_LOWB+CS_W+CS_AS+CS_SUSP
CSBAR10$ DC.W RAM2/256+B64K CS10 base & option register values
CSOR10$ DC.W 0*CS_WAIT+CS_UPPB+CS_W+CS_AS+CS_SUSP
* The next two words are used to modify the Module Configuration Register (MCR)
* per the formula shown below ( "[X]" = contents of location "X"):
* MCR = ([MCR].OR.[MCR_OR]).AND.[MCR_AND]
* Thus the power-on value of MCR is read, or'ed with MCR_OR, then and'ed with
* MCR_AND, and then stored back into MCR. This allows us to modify the default
* power-on value of MCR by adding bits we want and deleting bits we don't want!
* This process allows the user to remap the internal registers, since the MM bit
* is a write-once entity.
*
MCR_OR DC.W $020F Show cycles enabled, external arbitration
* enable, interrupt arbitration level = $F
* (highest priority).
MCR_AND DC.W $DFFF Enable bus monitor when FREEZE is asserted.
* and set Module Mapping (MM) to map internal
* modules to $FFF000-$FFFFFF.
*MCR_AND DC.W $DFBF Enable bus monitor when FREEZE is asserted
* and set Module Mapping (MM) to map internal
* modules to $7FF000-$7FFFFF.
SYPCR_OR DC.B $06 Bus Monitor External Enabled, 16 system clocks
SYPCR_AND DC.B $7F Disable Software Watchdog
*SYPCR_AND DC.B $FF Enable Software Watchdog
FCRYSTAL DC.W FCRYSTVAL Crystal frequency (in Hz)
FEXTAL DC.L FILL.4 External clock frequency (in Hz)
* ROM Auto Boot Vectors
RB_SP DC.L FILL.4 Allocate space for ROM BOOT SP and PC.
RB_PC DC.L FILL.4!1 . PC bit0= 1 disables ROM BOOT!
IFNE 4-(RB_PC-RB_SP)
FAIL 469 ROM BOOT SP/PC not adjacent anymore!
ENDC
* SCI Console Default Initialization Table (CONSCI)
*
CONSCI DS 0 * USE THIS FOR CONNECTION TO TERMINALS
*
******** Each bit set in '.PARMS' below enables the 7 parameters **********
******** that follow. DO NOT ALTER THE VALUE OF '.PARAMS' below! **********
*
.PARMS DC.L $1C0F
*
.BAUD DC.W 9600 Baud rate (in decimal)
.PARITY DC.B 0 Parity: $00= none, 'E'= even, 'O'= odd
.DATA DC.B 8 Nbr. data bits: 7 or 8
.STOP DC.B 1 Nbr. stop bits: 1 or 2
.XON_ENB DC.B $FF XON/XOFF enable:
* . $FF= enabled, $00= disabled
.XON DC.B $11 XON char: ^Q = $11
.XOFF DC.B $13 XOFF char: ^S = $13
*
* Periodic Interrupt Timer
* - assumes 32.768 KHz clock
*
.PICR DC.W TIMERLVL<<8+TIMERVEC Periodic int. control reg. value
* . Defines interrupt level & vector.
.PITR DC.W $0102 Periodic int. timing reg. value
* . Defines SYSCALL "tick" = 125 msec
* Power On Branch Vectors
* - There are no entry/exit restrictions for register usage here.
*
PWR_ON:
PWR_TBL1 BRA.L INIT_T1 Table #1 Initialization processing
* . - returns [A6]= Init Table #2 start addr
* . - returns to PWR_INI
PWR_INI BRA.L INIT_CS Initialize chip selects, etc. for 68332
* . - returns [D7.L]= Power Up Status Flag
* . - preserves [A6]
* . - returns to PWR_TBL2
PWR_TBL2 BRA.L INIT_T2 Table #2 Initialization processing
* . - entry [A6]= Init Table #2 start addr
* . - preserves [D7]
* . - returns to PWR_TTL
PWR_TTL BRA.L PWR_TST Print sign on message title.
* . - preserves [D7]
* . - returns to PWR_TST
* NOTE: PWR_TTL is not enabled yet. Signon message actually gets printed
* in SYSINIT routine via TRAP 15 calls! This may be changed in the
* future so simple SCI routines w/o stack usage can print messages
* until system has been verified (use address regs for return addrs).
*
PWR_TST BRA.L CONFTST Perform confidence tests.
* . - preserves [D7.L bits 8-31]
* . - returns [D7.B]= error code flag
* . - returns to PWR_GO
PWR_GO BRA.L SYSINIT Go start up the system.
* . - entry [D7.L bits 8-31]= Power Up
* . Status Flag
* . - entry [D7.B]= self-test error code flag
* . - never returns
DCB.W 2*3,FILL.2 Reserve space for 2 more BRA.L's (3 words each)
PWR_END EQU *
DCB.B 16,FILL.1 <reserved>
* Initialization Table Area:
* - see INITTBL.SA for description!
*
INITTBL DCB.B $A0,FILL.1
INITTBLE EQU * End of Init. Table.
* Sign On Message Test String
*
SIGNON DS.W 0
DC.B SIGN$2-SIGN$1 Set msg byte count
SIGN$1 DC.B CR,LF,LF
SIGN$3 DC.B 'CPU32Bug Debugger/Diagnostics - Version 1.00'
SIGN1SZ EQU *-SIGN$3 # chars in line #1 = $2D= 45
DCB.B 34,SPACE Pad to end of line (79-45= 34)
DC.B CR,LF
SIGN$4 DC.B ' (C) Copyright 1991 by Motorola Inc.'
SIGN2SZ EQU *-SIGN$4 # chars in line #2 = $24= 36
SIGN3SZ EQU ($200-(SIGNON-ORIGIN))-(*-SIGNON) Extra space= $17 = 23
DCB.B 23,SPACE Pad to end of sigon space
SIGN$2 EQU *
IFNE $200-(*-ORIGIN)
FAIL 499 Param area must= $200 to match user documentation!
ENDC
IFNE $08-(CODESIZE-ORIGIN)
FAIL 499 CODESIZE must= offset $08 to match user documentation!
ENDC
IFNE $0C-(SRECMAX-ORIGIN)
FAIL 499 SRECMAX must= offset $0C to match user documentation!
ENDC
IFNE $0E-(CHECKSUM-ORIGIN)
FAIL 499 CHECKSUM must= offset $0E to match user documentation!
ENDC
IFNE $10-(.CSBAR0-ORIGIN)
FAIL 499 .CSBAR0 must= offset $10 to match user documentation!
ENDC
IFNE $12-(.CSOR0-ORIGIN)
FAIL 499 .CSOR0 must= offset $12 to match user documentation!
ENDC
IFNE $3C-(.CSBARBT-ORIGIN)
FAIL 499 .CSBARBT must= offset $3C to match user documentation!
ENDC
IFNE $3E-(.CSORBT-ORIGIN)
FAIL 499 .CSORBT must= offset $3E to match user documentation!
ENDC
IFNE $40-(CSBAR0$-ORIGIN)
FAIL 499 CSBAR0$ must= offset $40 to match user documentation!
ENDC
IFNE $42-(CSOR0$-ORIGIN)
FAIL 499 CSOR0$ must= offset $42 to match user documentation!
ENDC
IFNE $6C-(MCR_OR-ORIGIN)
FAIL 499 MCR_OR must= offset $6C to match user documentation!
ENDC
IFNE $6E-(MCR_AND-ORIGIN)
FAIL 499 MCR_AND must= offset $6E to match user documentation!
ENDC
IFNE $70-(SYPCR_OR-ORIGIN)
FAIL 499 SYPCR_OR must= offset $70 to match user documentation!
ENDC
IFNE $71-(SYPCR_AND-ORIGIN)
FAIL 499 SYPCR_AND must= offset $71 to match user documentation!
ENDC
IFNE $72-(FCRYSTAL-ORIGIN)
FAIL 499 FCRYSTAL must= offset $72 to match user documentation!
ENDC
IFNE $74-(FEXTAL-ORIGIN)
FAIL 499 FEXTAL must= offset $74 to match user documentation!
ENDC
IFNE $78-(RB_SP-ORIGIN)
FAIL 499 RB_SP must= offset $78 to match user documentation!
ENDC
IFNE $7C-(RB_PC-ORIGIN)
FAIL 499 RB_PC must= offset $7C to match user documentation!
ENDC
IFNE $80-(.PARMS-ORIGIN)
FAIL 499 .PARMS must= offset $80 to match user documentation!
ENDC
IFNE $84-(.BAUD-ORIGIN)
FAIL 499 .BAUD must= offset $84 to match user documentation!
ENDC
IFNE $86-(.PARITY-ORIGIN)
FAIL 499 .PARITY must= offset $86 to match user documentation!
ENDC
IFNE $87-(.DATA-ORIGIN)
FAIL 499 .DATA must= offset $87 to match user documentation!
ENDC
IFNE $88-(.STOP-ORIGIN)
FAIL 499 .STOP must= offset $88 to match user documentation!
ENDC
IFNE $89-(.XON_ENB-ORIGIN)
FAIL 499 .XON_ENB must= offset $89 to match user documentation!
ENDC
IFNE $8A-(.XON-ORIGIN)
FAIL 499 .XON must= offset $8A to match user documentation!
ENDC
IFNE $8B-(.XOFF-ORIGIN)
FAIL 499 .XOFF must= offset $8B to match user documentation!
ENDC
IFNE $8C-(.PICR-ORIGIN)
FAIL 499 .PICR must= offset $8C to match user documentation!
ENDC
IFNE $8E-(.PITR-ORIGIN)
FAIL 499 .PITR must= offset $8E to match user documentation!
ENDC
IFNE $90-(PWR_ON-ORIGIN)
FAIL 499 PWR_ON must= offset $90 to match user documentation!
ENDC
IFNE $90-(PWR_TBL1-ORIGIN)
FAIL 499 PWR_TBL1 must= offset $90 to match user documentation!
ENDC
IFNE $96-(PWR_INI-ORIGIN)
FAIL 499 PWR_INI must= offset $96 to match user documentation!
ENDC
IFNE $9C-(PWR_TBL2-ORIGIN)
FAIL 499 PWR_TBL2 must= offset $9C to match user documentation!
ENDC
IFNE $A2-(PWR_TTL-ORIGIN)
FAIL 499 PWR_TTL must= offset $A2 to match user documentation!
ENDC
IFNE $A8-(PWR_TST-ORIGIN)
FAIL 499 PWR_TST must= offset $A8 to match user documentation!
ENDC
IFNE $AE-(PWR_GO-ORIGIN)
FAIL 499 PWR_GO must= offset $AE to match user documentation!
ENDC
IFNE $D0-(INITTBL-ORIGIN)
FAIL 499 INITTBL must= $D0 to match user documentation!
ENDC
IFNE $170-(INITTBLE-ORIGIN)
FAIL 499 INITTBLE must= $170 to match user documentation!
ENDC
IFNE $170-(SIGNON-ORIGIN)
FAIL 499 SIGNON must= $170 to match user documentation!
ENDC
END